clock flip-flop

基本解释

With the mechanism of clock flip- flop, data can be extracted automatically.
系統採用時鍾觸發機制實現了數據的自動抽取過程；
Especially, the clock-racing multi-threshold flip-flop can decreases the leakage power and the power dissipation of clock network.
特別是多閾值時鍾競爭型觸發器，不僅可以降低電路的漏電流功耗，還能降低電路的時鍾網絡的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模擬結果表明所設計的觸發器具有正確的邏輯功能，跟傳統的時鍾低擺幅雙邊沿觸發器相比，降低近17%的功耗。