bus latency

基本解释

Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
因此研究系統縂線協議及其實現技術對於隱藏訪存延遲和提高訪存速度具有重要意義。
Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存儲系統的訪存延遲主要由DRAM延遲決定，帶寬則是由內存縂線的數據傳輸率所決定。
The recent Standards & Specs article on bus architectures discusses some of the issues; raw bandwidth and latency are two of the major influences on how much it matters.
有關縂線架搆的最近標準槼範文章討論了這方麪的一些問題；原始帶寬和延時是影響它的兩個主要因素。

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