bus latency

基本解释

• [计算机科学技术]总线等待时间

英汉例句

双语例句

• Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
  因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。
• Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
  片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。
• The recent Standards & Specs article on bus architectures discusses some of the issues; raw bandwidth and latency are two of the major influences on how much it matters.
  有关总线架构的最近标准规范文章 讨论了这方面的一些问题；原始带宽和延时是影响它的两个主要因素。

权威例句

• Residing directly on the PCIe bus, this new addition to the Vector Series provides lower latency to data, faster file transfers and boot-ups, expanded storage capacities, and an even quicker, more responsive experience over the already blazing fast SATA III-based Vector SSDs.
  ENGADGET: OCZ demos Vector SSD in even speedier PCI Express form for the pros

• bus latency更多例句

词组短语

短语

• bus acquisition latency 总线获取等待时间
• bus access latency 总线访问延时
• memory input bus latency time 存储器等待时间

• bus latency更多词组

专业释义

计算机科学技术

• 总线等待时间